Field of the Invention
The invention relates to producing fine structures on substrates in lithographic methods for producing structures of microelectronic components by using projection exposure. The invention also relates to a computer program for executing a method for optimizing and a method for producing a layout for a mask.
The wavelengths used in projection exposure are nowadays greater than the smallest dimensions of the structures to be produced on the substrate. Therefore, diffraction effects play a major part in imaging the structures. Diffraction effects flatten the intensity gradient at the edge of a structure because of light being scattered during the exposure of closely adjacent structures.
The unsharpness (i.e. fuzziness) of edges that are produced thereby and the resulting size distortion depend in principle on the relative proximity of the structures on the substrate, the optical wavelength, and the numerical aperture of the exposure device. Thus, given the same exposure (that is to say the same wavelength and numerical aperture), two structures that actually have the same dimensions exhibit different dimensions following exposure, depending on how closely these structures lie to other parts of the exposed layout. The phase and coherence of the light also has an influence. This change in the size relationships as a function of the relative proximity of the structures is called the xe2x80x9cproximity effectxe2x80x9d.
In order to reduce the proximity effect, it is known to carry out an optical proximity correction (OPC) of the structure before creating the mask. An OPC is conducted to ensure that the finished structures on the substrate actually have the sizes envisaged in the layout. The sizes are not obvious because, during the production of a microelectronic component, size changes may occur (for example as a result of the proximity effect mentioned). These are compensated by the OPC.
In that case, the OPC can be conducted by using a simulation program (simulation-based OPC) or a rule-based software system (rule-based OPC).
In order to improve the sharpness of the image in lithography, U.S. Pat. No. 5,242,770 issued to Chen et al. additionally discloses the practice of applying thin lines between the structures on the mask. These lines are so thin that they are not themselves imaged on the substrate by exposure. These scatter bars, as they are known, influence the intensity gradients at the edges of the structures, so that differences between closely packed parts of the structure and further spaced parts of the structures are compensated for. In this case, the scatter bars are disposed at predeterminable intervals parallel to parts of the structure. When placing the scatter bars, an intended ideal distance from the main structures is maintained when compatible with the layout.
The size reduction in semiconductor production has in the meantime progressed so far that structure sizes are smaller than the wavelength of the light used in the lithographic step. The smaller the structure sizes, the more important it is to modify the layouts by using OPC before mask production to account for diffraction effects during the optical imaging.
When the two methods are combined (OPC and scatter bars), however, the following difficulty arises because of their mutual effect: simulation-based OPC has to be carried out while accounting for the lithographic influence of the scatter bars, for which reason the latter has to be generated in the original layout before the correction. Because the dimensions of the main structures are changed by the OPC, deviations in the distances between main structures and scatter bars from the desired ideal distance occur simultaneously. If the scatter bars move too closely to the main structures, then their optical influence becomes so high that the exposure and fabrication tolerances lead to uncontrollable results; on the other hand, if they move too far away, then their positive influence on the process window is lost.
These problems have hitherto been solved by the distance of the scatter bars from the main structures in the original layout (before the correction) having been chosen to be so large that, with the maximum permissible broadening of the main structures as a result of OPC, a necessary minimum distance of the scatter bars from the corrected main structures was guaranteed. As a result, an undesirably large distance from the main structures was produced for the majority of these scatter bars. This forfeits some of the positive influence on the process window.
It is accordingly an object of the invention to provide a method for optimizing and a method for producing a layout for a mask, preferably for use in semiconductor production, and a computer program therefor, that overcome the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that reduce the problems in the prior art.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method of optimizing a layout for a mask for use in semiconductor production. The layout has main structures and scatter bars. The method includes the following steps. The first step is (a) defining one or more of the main structures. The next step is (b) defining one or more of the scatter bars in accordance with predetermined rules. The next step is (c) carrying out an OPC on the main structures while accounting for the scatter bars. The next step is (d) comparing the corrected main structures with the main structures before step (c). The next step is (e) repeating steps (b) to (e) based on the corrected main structures, depending on the comparison in step (d). In the following text, the above-described method will be designated xe2x80x9cIteration Axe2x80x9d.
The scatter bars can consequently be iteratively matched optimally to the main structures corrected by using OPC by using the method of the invention.
In particular, the comparison in step (d) can be a comparison of the layers of the main structures, and the definition of the scatter bars in step (b) can be carried out on the basis of the position of the main structures and, when step (b) is repeated, on the basis of a mean value along the edges of the main structures before and after the preceding OPC. As a result, it is possible to avoid, for example, a situation where the scatter bars running along the edges of the corrected main structures are divided into excessively small portions. For instance, in the case of only slight fluctuations in the width of a corrected structure, it is expedient to calculate a mean value relative to which the position of a scatter bar can then be defined.
In general, the iteration should be terminated when the maximum or mean distance of the main structures between two successive iteration steps lies below a predefinable threshold value.
In one refinement of the invention, steps (b) to (e) are repeated if the largest change in a parameter as a result of OPC lies above a predetermined threshold value. By suitably defining the threshold value, the level of optimization of the method to the requirements in semiconductor production can be adapted individually. In this case, the parameter is advantageously a distance between two main structures. An alternative or additional termination criterion can be defined by the OPC grid, that is to say the iteration is terminated as soon as the variation between two successive iteration steps lies below the resolution of the OPC grid.
In another refinement, steps (b) to (e) are repeated only when the main structures do not remain unchanged by the OPC. In this refinement, a higher number of iterations is generally necessary, but this results in a higher level of optimization.
Depending on the refinement, when step (b) is repeated, the position and/or the dimensions of one or more of the scatter bars may be changed. Likewise, during the OPC, the position and/or the dimensions of one or more of the main structures may be changed.
In summary, the iteratively generated scatter bars possess the ideal spacing from the main structures. As a result, the positive influence comes to bear fully on the process window, otherwise than in the case of known methods. At the same time, the danger of falling below the necessary minimum distance of the scatter bars from the main structures is ruled out.
The method can be employed generally for the production of scatter bars, irrespective of its specific software implementation or the OPC and with only slightly widened rules.
With the objects of the invention in view, there is also provided a method of producing a layout for a mask for use in semiconductor production, the layout having main structures and scatter bars, having the following steps:
(axe2x80x2) or (f) simulating a defocused exposure of the mask for imaging at least one of the main structures;
(bxe2x80x2) or (g) comparing the main structures obtained in step (axe2x80x2) or (f) with reference main structures; and
(cxe2x80x2) or (h) varying at least one of the scatter bars and repeating steps (axe2x80x2) or (f) to (cxe2x80x2) or (h) based on the comparison in step (bxe2x80x2) or (g).
In the following text, the above-described method will be designated xe2x80x9cIteration Bxe2x80x9d.
As a result of Iteration B, according to the invention, the scatter bars are consequently optimized with regard to possible defocusing of the light during lithography. Such defocusing can occur, for example, on account of irregularities on the surface of wafers, as a result of which the distance between wafer surface and light source varies.
In particular, Iteration B permits refinement of the structures created by Iteration A: the corrections explained in conjunction with Iteration A are carried out under xe2x80x9cbest focusxe2x80x9d conditions, as they are known: that is, under the assumption that the light used to expose the mask is focused optimally onto the wafer lying underneath. The ideal distance of scatter bars from the main structures is distinguished by the fact that the lithographic imaging of the main structures remains as stable as possible even in the event of defocusing: that is, approximately independent of the focusing over a certain area. Iteration B is based on the finding that this ideal state is not constant for all situations but depends on the structure width and the position of other adjacent structures.
Therefore, Iteration B can optimize the distances obtained by Iteration A and determined for the ideal state (best possible focusing) further for possible defocusing during the actual semiconductor production. This means that, through Iteration B, optimization is achieved irrespective of the ideal focusing. Iteration B can therefore advantageously follow Iteration A directly.
In step (axe2x80x2) or (f), a simulation of a defocused exposure of the mask at the edge of the process window is advantageously carried out. The edge of the process window designates that area which a predefined tolerance of the structure width because of defocusing is just still maintained. Therefore, defocusing at the edge of the process window also comes to bear to the greatest extent.
Step (axe2x80x2) or (f) is additionally advantageously repeated with different defocusings. In step (bxe2x80x2) or (g), each of the main structures obtained with different defocusings are compared with the reference main structures. In this way, optimization of the scatter bars for different defocusings can be achieved, which results in a greater tolerance with respect to wafer irregularities during semiconductor production.
Steps (axe2x80x2) or (f) to (cxe2x80x2) or (h) are advantageously repeated when the greatest change in the parameter of the main structures with respect to the reference main structures lies above a predetermined threshold value. By defining the threshold value, the tolerance of the layout with respect to focusing fluctuations during production can be controlled.
The reference main structures are preferably formed by the initial main structures in the layout configuration. Alternatively, the reference main structures can also be formed by xe2x80x9ctargetsxe2x80x9d on the wafer.
The optimization of the scatter bars is preferably averaged for the various simulated defocusings, so that the most far-reaching independence of the focusing actually established during the production results.
The parameter is preferably a distance between a main structure and a reference main structure, and the comparison in step (bxe2x80x2) or (g) is a comparison of the edges of the main structures.
In one refinement, during variation of the scatter bars in step (cxe2x80x2) or (h), a displacement of one or more of the scatter bars by an amount proportional to the difference between the simulated width of one or more of the main structures and one or more predetermined threshold values is carried out. As a result, the number of iteration steps necessary for the optimization can be reduced.
During variation of at least one of the scatter bars in step (cxe2x80x2) or (h), the position and/or the dimensions of the at least one scatter bar can be varied.
As already mentioned above, an Iteration A is preferably followed by an Iteration B. Iteration A can then be carried out, followed by a further Iteration B. With each iteration, the layout is optimized further and therefore an enlargement of the usable process window is achieved. Further subsequent Iterations A and B are possible. Termination conditions that correspond to sufficient optimization of the layout preferably are defined for this purpose.
According to the invention, a computer program is additionally created to execute the method steps described above on a computer. The possibility of optimizing a semiconductor layout by computer simulation is therefore provided.
In summary, it should be noted that the common factor in both iterations is that the position of the scatter bars is varied and therefore optimized with each iteration step, specifically on the basis of a comparison of corrected (Iteration A) or simulated (Iteration B) main structures with reference structures (for example the main structures before correction in the case of Iteration A, or initial structures in the case of Iteration B).
Moreover, according to the invention, a method is provided for producing a semiconductor layout having at least one main structure and at least one scatter bar. The method has the following steps. The first step is (a) defining the position and/or dimensions of the main structure. The next step is (b) defining the position and/or dimensions of the scatter bar relative to those of the main structure. The next step is (c) carrying out an OPC of the main structure, taking account of the scatter bar. The next step is (d) comparing the position and/or dimensions of the main structures before and after step (c). The next step is (e) repeating steps (b) to (e) based on the corrected main structure, if the position and/or dimensions of the main structure before step (c) differ from those after step (c) by more than one or more predetermined values. The next step is (axe2x80x2) or (f) simulating a defocused image of the main structure by exposing the layout. The next step is (bxe2x80x2) or (g) comparing the position and/or dimensions of the simulated defocused image of the main structure with one or more predetermined values. The next step is (cxe2x80x2) or (h) varying the length and/or dimensions of the scatter bar and repeating steps (axe2x80x2) or (f) to (cxe2x80x2) or (h) if this deviation in the position and/or dimensions of the simulated defocused image of the main structure from the predetermined values is greater than a likewise predetermined further value.
In this method, Iterations A and B are combined for the most far-reaching optimization.
As indicated further above, the predetermined values can depend on the original structures in the layout configuration or else on targets for the wafer.
With the objects of the invention in view, there is also provided a computer program for executing the above-described methods on a computer.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for optimizing and method for producing a layout for a mask, preferably for use in semiconductor production, and computer program therefor, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.